Software makes the link with verification

EDA Simulator Link DS lets design, verification and system engineers use Matlab and Simulink to efficiently model, analyse and verify HDL and RTL implementations.

The MathWorks has announced the availability of EDA Simulator Link DS, which provides a cosimulation link between Matlab and Simulink and the Synopsys VCS MX functional verification solution.

EDA Simulator Link DS enables reuse of system-level models as test benches for hardware description language (HDL) and register transfer level (RTL) implementations by co-ordinating the execution of Synopsys' VCS MX solution with Matlab code and Simulink models.

This integration accelerates functional verification by automating stimulus and response generation between the two environments, reducing manual recoding of test benches and providing enhanced debugging capabilities to system and verification engineers.

Engineers using Synopsys' VCS MX functional verification solution can now use EDA Simulator Link DS to improve product quality and reduce verification time and costs.

EDA Simulator Link DS lets design, verification and system engineers use Matlab and Simulink to efficiently model, analyse and verify HDL and RTL implementations.

Key features include: full VHDL, Verilog and mixed-language cosimulation support; Matlab test bench capability, enabling the use of Matlab code to stimulate HDL code and check its response; Matlab component capability, enabling simulation of Matlab code in place of entities not yet coded in HDL; user-selectable shared-memory and TCP/IP-socket communications modes; and interactive or batch mode co-simulation, debugging, testing and verification of HDL.

EDA Simulator Link DS is available now.

UK list prices start at GBP 1400 plus VAT for an individual licence.

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